Dq Group Assignment Examples

Description

The MIG 7 Series tool allows users to select specific Byte Groups within an FPGA Bank for Data and Address/Control groups.The tool does not allow users to select the specific pins within those byte groups. If the pin-out generated by MIG does not follow the desired pin-out on my board, how can the design be modified?

Starting with MIG 7 Series 1.2 (available with ISE 13.2), the tools include the Verify UCF and Update Design and UCF feature. This feature allows users to input a UCF with the desired pin-out and have MIG generate the appropriate design and UCF files.

For MIG 7 Series 1.1, users need to ensure that the correct Byte Group assignments are made in the MIG generated design. From there, this Answer Record details the steps to move pins within a byte group. For example, the data group associated with DQS[0] must be assigned to the appropriate Byte Group TX within the tool. This Answer Record shows the manual changes required to swap DQ[0] with DQ[7] (as an example) in the generated design.

Design Overview

This page describe how to implement an 8-bit wide, 150-MHz, 300-Mbps DDR2 SDRAM full-rate interface using the ALTDQ_DQS megafunction integrated with a few other megafunctions. The design targets the EP3SL150F1152C2 device, and an 8-bit wide 256-MB Micron MT47H32M8BP-3:B 333 MHz DDR2 SDRAM component.

Design Specifications

The design specifications are listed in the table below.

Attribute Specification
Quartus II version 11.0 
FPGA device EP3SL150F1152C2
External memory device DDR2 SDRAM (Micron MT47H32M8BP-3:B)
External memory speed 333 MHz
IP used ALTDQ_DQS, ALTPLL, ALTDLL, ALTIOBUF

Figure 1 shows the example interface between the Stratix III EP3SL150F1152C2 device and an 8-bit wide 256-MB Micron MT47H32M8BP-3:B 333-MHz DDR2 SDRAM component. The CK, CK_N, CK_E, CS_N, RAS_N, CAS_N, WE_N, ODT, DM, BA[2:0], and ADDR[14:0] signals are output-only signals. DQ[7:0], DQS and DQS_N are bidirectional signals.

Design Generation

This section describes the steps required to instantiate a custom physical layer (PHY) implemented using Altera's megafunctions, as well as a custom designed controller. This design example is in Verilog HDL and consists of one top-level module or instance that connects 19 sub-modules or instances for a complete customized DDR2 interface with an SDRAM.

Create a Quartus II Project

Create a project in the Quartus II software that targets the EP3SL150F1152C2 device by performing the following steps.

  1. Open the altdll_altdq_dqs_DesignExample_ex1.zip file and extract the altdll_altdq_dqs_design_ex1.qar file.
  2. In the Quartus II software, restore the altdll_altdq_dqs_design_ex1.qar file into your working directory.
  3. Open the altdll_altdq_dqs_design_ex1.bdf file.

Generate the ALTPLL Megafunction

This design example uses the ALTPLL megafunction to implement two PLLs that clock the entire full-rate interface. Use the MegaWizard Plug-In Manager to instantiate two ALTPLL megafunctions with the following parameters:

pll_1:

  • in_clock = 50 MHz
  • mode = no compensation
  • c0 = 150 MHz, 0° phase shift. Used to clock the dll_1 instance. This PLL is dedicated to clock only the DLL.


pll_2:

  • in_clock = 50 MHz
  • mode = normal
  • c0 = 150 MHz, 0° phase shift. This is the mem_clk. It is used to clock the registers in the altdq_dqs_1 instance (the DQS output registers, the DQS OE registers, the DQS dynamic OCT registers, and DQ dynamic OCT registers), in the mem_clock_generate instance (the registers for generating CK and CK_N signals), the control_init_ddr instance (state machine for initialization of the DDR2), the control_write_ddr instance (state machine for writing data to the DDR2), the control_read_ddr instance (state machine for reading data from the DDR2), and the control_driver_ddr instance (state machine for driving the control_init_ddr instance, control_write_ddr instance, and control_read_ddr instance). It is also used to clock the registers in the addr_cmd_generate and addr_cmd_generate_oe instances which are used to generate the ADDR[14:0], BA[2:0], CK_E, CS_N, RAS_N, CAS_N, WE_N, and ODT signals.
  • c1 = 150 MHz, –90° phase shift. This is the write_clk. It is used to clock the registers in the altdq_dqs_1 instance (the DQ output registers and the DQ OE registers). 

Generate the ALTDLL Megafunction

This design example uses the ALTDLL megafunction to instantiate a DLL of the correct operational frequency (DQS signal frequency) of the custom external memory. This frequency setting depends on the bandwidth you want. Use the MegaWizard Plug-In Manager to instantiate a variations of the ALTDLL megafunction with the following parameters:

dll_1:

  • turn on jitter reduction = No
  • delay chain length = 12
  • delay buffer mode = low
  • DQS input frequency = 150 MHz
  • Instantiate DLL offset control A = No
  • Instantiate DLL offset control B = No
  • create ‘dll_aload’ port = No
  • create ‘dll_dqsupdate’ port = Yes

Generate the ALTDQ_DQS Megafunction

Next, you configure the settings for the dedicated circuitry for external memory interfaces using the ALTDQ_DQS megafunction. This custom DDR2 external memory interface consists of the following:

  • One pair of differential DQS/DQSn I/O pin (read or write strobe/clock)
  • Eight DQ I/O pins (read or write data)
  • One DM pin (output-only data mask)

The following section describes how to instantiate a variation of the ALTDQ_DQS megafunction with the correct parameter settings on each individual pages of the ALTDQ_DQS MegaWizard Plug-In Manager.

Page 3: Parameter Settings page

Page 3 of the ALTDQ_DQS MegaWizard Plug-In Manager is the Parameter Settings page. To configure the general settings for the ALTDQ_DQS instance, specify the options shown in the table below.

Option Value
Number of bidirectional DQ 8. There are 8 bidirectional DQ pins.
Number of input DQ 0. Not used.
Number of output DQ 1. There is 1 output only DM pin.
Number of stages in dqs_delay_chain 3. This enables the DQS strobe signal to be centered with the DQ data (DQS signal must be +90° phase shifted)
DQS input frequency Enter 150 MHz
Use half-rate components Turn off this option.
Use dynamic OCT path Turn off this option.


Page 4: DQS IN Advanced Options page 

Page 4 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQS IN Advanced Options page. To configure the DQS input path of the ALTDQ_DQS instance, set the options shown in Table 2–2.

Option Value
Enable DQS Input Path Turn on this option.
Delay chain usage: Select the Enable dqs_delay_chain option.
Advanced Delay Chain Options (DQS Delay Chain Phase Setting Options) Turn off the Select dynamically using configuration registers option.
Advanced Delay Chain Options (DQS Delay Chain Phase Setting Options) Select the DLL option.
Advanced Delay Chain Options (DQS Delay Buffer Mode) Select the Low option.
Advanced Delay Chain Options (DQS Phase Shift) Enter 9,000.
Advanced Delay Chain Options (Enable DQS offset control) Turn off this option.
Advanced Delay Chain Options (Enable DQS delay chain latches) Turn on this option.
Enable DQS busout delay chain Turn on this option.
Enable DQS enable block Turn on this option.
Enable DQS enable control block Turn on this option.
Advanced Enable Control Options (DQS Enable Control Phase Setting) Select the Set statically to ‘0’ option.
Advanced enable control options (DQS Enable Control Invert Phase) Select the Never option.
Enable DQS enable block delay chain Turn on this option.

 

Page 5: DQS OUT/OE Advanced Options page 

Page 5 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQS OUT/OE Advanced Options page. To configure the DQS OUTPUT and DQS OE path of the ALTDQ_DQS instance, select the options shown in Table 2–3.

Option Value
Enable DQS output path Turn on this option
DQS Output Path Options (Enable DQS output delay chain1) Turn on this option
DQS Output Path Options (Enable DQS output delay chain2) Select the DDIO option
DQS Output Path Options (DQS output register mode)  Select the DDIO option
DQS Output Enable Options (Enable DQS output enable) Turn on this option
DQS Output Enable Options (Enable DQS output enable delay chain1) Turn on this option
DQS Output Enable Options (Enable DQS output enable delay chain2) Turn on this option
DQS Output Enable Options (DQS output enable register mode) Select the FF option

 

Page 6: DQ IN Advanced Options page

Page 6 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQ IN Advanced Options page. To configure the DQ input path of the ALTDQ_DQS instance, select the options shown in Table 2–4.

Option Value
DQ Input Register Options (DQ input register mode) Select DDIO option.
DQ Input Register Options (DQ input register clock source) Select the ‘dqs_bus_out’ port option and disable the
‘Connect DDIO clkn to DQS_BUS from complementary DQSn’ option.
DQ Input Register Options (Use DQ input phase alignment) Turn on this option
Advanced DQ IPA options:(DQ Input Phase Alignment Phase Setting)

Select the Set statically to ‘0’ option.

Advanced DQ IPA options: (Add DQ Input Phase Alignment Input Cycle Delay) Select the Never option.
Advanced DQ IPA options: (Invert DQ Input Phase Alignment Phase) Select the Never option.
Advanced DQ IPA options: (Register DQ input phase alignment bypass output) Turn on this option
Advanced DQ IPA options: (Register DQ input phase alignment add phase transfer) Turn on this option
DQ Input Register Options (Use DQ half rate ‘dataoutbypass’ port) Turn on this option
Use DQ input delay chain Turn on this option


Page 7: DQ OUT/OE Advanced Options page

Page 7 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQ OUT/OE Advanced Options page. To configure the DQ OUTPUT and DQ OE path of the ALTDQ_DQS instance, select the options shown in Table 2–5.

Option Value
DQ Output Path Options (Enable DQ output delay chain1) Turn on this option
DQ Output Path Options (Enable DQ output delay chain2) Turn on this option
DQ Output Path Options (DQ output register mode) Select the DDIO option
DQ Output Enable Options (Enable DQ output enable) Turn on this option
DQ Output Enable Options (Enable DQ output enable delay chain1) Turn on this option
DQ Output Enable Options (Enable DQ output enable delay chain2) Turn on this option
DQ Output Enable Options (DQ output enable register mode) Select the FF option


Page 8: Half-rate Advanced Options page

Page 8 of the ALTDQ_DQS MegaWizard Plug-In Manager is the Half-rate Advanced Options page. To configure the half-rate settings of the ALTDQ_DQS instance, select the options shown in Table 2–6.

Option Value
IO Clock Divider Source Turn off this option. This option is not applicable for full-rate interface.
Create ‘io_clock_divider_masterin’ input port Turn off this option. This option is not applicable for full-rate interface.
Create ‘io_clock_divider_clkout’ output port Turn off this option. This option is not applicable for full-rate interface.
Create ‘io_clock_divider_slaveout’ output port Turn off this option. This option is not applicable for full-rate interface.
IO Clock Divider Invert Phase Select the Never option. Not applicable for fullrate interface

Page 9: OCT Path Advanced Options page

Page 9 of the ALTDQ_DQS MegaWizard Plug-In Manager is the OCT Path Advanced Options page. To configure the OCT registers and delay chain settings of the ALTDQ_DQS instance, select the options shown in Table 2–7.

Option Value
Dynamic OCT Options (Enable OCT delay chain 1) Turn off this option. This option is not applicable for full-rate interface.
Dynamic OCT Options (Enable OCT delay chain 2) Turn off this option. This option is not applicable for full-rate interface.
DQ Output Path Options (OCT register mode) Turn off this option. This option is not applicable for full-rate interface.


Page 10: DQS/DQSn IO Advanced Options page

Page 10 of the ALTDQ_DQS MegaWizard Plug-In Manager is the DQS/DQSn IO Advanced Options page. Select options shown in Table 2–8.

Option Value
Use DQSn I/O Turn on this option.
DQS and DQSn IO Configuration mode Select the Differential Pair option. This is required for this particular scenario.


Page 11: Reset Ports Advanced Options page

Page 11 of the ALTDQ_DQS MegaWizard Plug-In Manager is the Reset Ports Advanced Options page. Select options shown in Table 2–9.

Option Value
Create ‘dqs_areset’ input port Turn on this option
Create ‘dqs_sreset’ input port Turn off this option
Create ‘input_dq_areset’ input port Turn off this option
Create ‘input_dq_sreset’ input port Turn off this option
Create ‘output_dq_areset’ input port Turn on this option
Create ‘output_dq_sreset’ input port Turn off this option
Create ‘bidir_dq_areset’ input port Turn on this option
Create ‘bidir_dq_sreset’ input port Turn off this option

Generate the ALTIOBUF Megafunction

For an external memory interface, the DQ, DQS, DQSn, DM, ADDR[14:0], BA[2:0], CK, CK_N, CK_E, CS_N, RAS_N, CAS_N, WE_N, and ODT pins must be connected to I/O buffers via the ALTIOBUF megafunction. There are 14 interface signals for this design example that need I/O buffers to be interfaced with the FPGA pins. These I/O buffers are contained in the dqs_io_buffer, ck_io_buffer, dq_io_buffer, dm_io_buffer, addr_io_buffer, ba_io_buffer, and cmd_io_buffer instances. There are 35 I/O buffers used in this instance. Table 2–10 shows the requirements that must be set for these signals in the I/O buffer instances.

Signal Instance Requirement
DQS and DQS_N  dqs_io_buffer 1-bit bidirectional I/O buffer with differential capabilities enabled
CK and CK_N ck_io_buffer 2-bit output I/O buffer with differential capabilities enabled
DQ[7:0] dq_io_buffer 8-bit bidirectional I/O bufferI/O buffer
DM dm_io_buffer 1-bit output I/O buffer
ADDR[14:0] addr_io_buffer 15-bit output I/O buffer
BA[2:0] ba_io_buffer 3-bit output I/O buffer
CK_E cmd_io_buffer 1-bit output I/O buffer
CS_N cmd_io_buffer 1-bit output I/O buffer
RAS_N cmd_io_buffer 1-bit output I/O buffer
CAS_N cmd_io_buffer 1-bit output I/O buffer
WE_N cmd_io_buffer 1-bit output I/O buffer
ODT cmd_io_buffer 1-bit output I/O buffer

Design Customized Memory Controller Datapath Logic

Because this is a custom external memory interface for DDR2 interface, you must design the necessary datapath to control the CK, CK_N, ADDR[14:0], BA[2:0], CK_E, CS_N, RAS_N, CAS_N, WE_N, and ODT signals. Altera provides a design example that you can use to create your own logic. In the Altera-provided design example, the datapath of the CK and CK_N signals are controlled by the mem_clock_generate instance. This instance consists of two DDIO_OUT blocks. For the CK signal, the inputs of the DDIO_OUT block are each tied to VCC and GND. For the CK_N signal, the inputs of the DDIO_OUT block are each tied to GND and VCC to reflect the inverse of the CK signal. The addr_cmd_generate instance controls the datapath of the ADDR[14:0], BA[2:0], CK_E, CS_N, RAS_N, CAS_N, WE_N, and ODT signals. This ddr_cmd_generate instance consists of 24 DDIO_OUT blocks to individually represent the 24 signals. For these signals, there are 24 DFF blocks to control their respective OE (output enable) signals. The OE signals are controlled by the addr_cmd_generate_oe instance. The inputs of these 48 blocks are fed accordingly with data, depending on the three state machines that act as the control path of the customized memory controller. The three state machines are as follows:

  • control_init_ddr instance
  • control_write_ddr instance
  • control_driver_ddr instance

Multiplexer Instances

There are two multiplexer instances: cmd_addr_mux_1 and dqs_dqsn_dq_dm_mux_1.

cmd_addr_mux_1

The cmd_addr_mux_1 instance is a 144-bit to 72-bit multiplexer with a 1-bit select signal. The cmd_addr_mux_1 instance multiplexes the CK_E, CK_N, RAS_N, CAS_N, WE_N, BA_OE, BA_DATA, ADDR_OE, ADDR_DATA and ODT signals from the following two control path state machines of the customized memory controller: 

  • control_init_ddr instance
  • control_write_ddr instance

The output of the multiplexer is sent to the data path of the command and address instances, addr_cmd_generate and addr_cmd_generate_oe. For this multiplexer, the control_driver_ddr instance controls the 1-bit select.

dqs_dqsn_dq_dmr_mux_1

The dqs_dqsn_dq_dmr_mux_1 instance is a 66-bit to 33-bit multiplexer with a 1-bit select signal. The dqs_dqsn_dq_dmr_mux_1 instance multiplexes the dm_oe, dm_data, dq_oe, dq_data, dqs_oe, dqs_data, dqsn_oe, and dqsn_data signals from the following two control path state machines of the customized memory controller:

  • control_init_ddr instance
  • control_write_ddr instance

The output of the multiplexer is sent to the data path of the DQS, DQSN, DQ, and DM (ALTDQ_DQS instance), which is the altdq_dqs_1 instance. The 1-bit select for this multiplexer is controlled by the control_driver_ddr instance. This completes the steps for the customized memory controller datapath logic to generate the CK,CK_N, ADDR[14:0], BA[2:0], CK_E, CS_N, RAS_N, CAS_N, WE_N, and ODT signals.

Design Customized Memory Controller Control Path Logic

Because this is a custom external memory interface for the DDR and DDR2 interface, you must design control path logic to control the DQS, DQS_N, DQ, DM, A (address), BA (bank address), CK, CK#, CKE, CS#, RAS#, CAS#, WE#, and ODT signals from the FPGA core. The design example contains three state machines to control these signals to enable proper operation of the external memory interface. These state machines are as follows:

  • control_init_ddr instance

The control_init_ddr instance initializes the DDR2 component for the proper interface operation following the timing requirements as specified in the specific Micron DDR2 datasheet. Because the ALTMEMPHY megafunction does not support a burst length of 8, the customized memory controller in this design example initialized the DDR2 for this mode of operation.

  • control_write_ddr instance

The control_write_ddr instance writes a set of 8 data to the memory array in the DDR2 component following the timing requirements as specified in the specific Micron DDR2 datasheet.

  • control_driver_ddr instance

The control_driver_ddr instance coordinates the two state machines (control_init_ddr and control_write_ddr instances) following the timing requirements as specified in the specific Micron DDR2 datasheet to enable proper operation of this design example. This includes sequentially enabling the following instances:

  • The control_init_ddr instance state machine to initialize the DDR2 component
  • The control_write_ddr instance state machine to write the data to the memory array in the DDR2 component

The state machine also controls the select signals of the two multiplexers (cmd_addr_mux_1 and dqs_dqsn_dq_dm_mux_1) depending on which of the two control path state machine is currently active.

Add Constraints

After instantiating the necessary instances to create a customized DDR2 memory controller from the “Instantiate PHY (via ALTDLL and ALTDQ_DQS) and (Custom-Designed) Controller in a Quartus II Project” stage, you must generate the constraints files for the design example. Apply these constraints to the design before compilation. You must manually specify constraints because this design example does not use the ALTMEMPHY megafunction or the DDR2 SDRAM high-performance controller.

Add Timing Constraints

When you instantiate the customized DDR2 memory controller design, it does not automatically generate a timing constraint file (SDC file). You must manually create your own SDC file to constrain the timing on this design. This design example comes with a timing constraints file, top_custom_ddr2_controller_phy_ddr_timing.sdc. The timing constraint file constrains the clocks on the customized DDR2 memory controller design. To add timing constraints, perform the following steps:

  1. On the Assignments menu, click Settings.
  2. In the Category list, expand Timing Analysis Settings and select TimeQuest Timing Analyzer.
  3. Select the top_custom_ddr2_controller_phy_ddr_timing.sdc file and click Add.
  4. Click OK.

Set Optimization Technique

To ensure the remaining unconstrained paths are routed with the highest speed and efficiency, set the optimization technique to Speed. To set the optimization technique, perform the following steps:

  1. On the Assignments menu, click Settings.
  2. Select Analysis & Synthesis Settings.
  3. Under Optimization Technique, select Speed.
  4. Click OK.

Set Fitter Effort

To set the Fitter effort to Standard Fit, perform the following steps:

  1. On the Assignments menu, click Settings.
  2. Expand Fitter Settings.
  3. Turn on Optimize Hold Timing and select All Paths.
  4. Turn on Optimize Fast Corner Timing.
  5. Under Fitter Effort, select Standard Fit.
  6. Click OK.

Enter Pin Location Assignments

To enter the pin location assignments, perform the following steps:

  1. On the Processing menu, point to Start, and click Start Analysis and Synthesis.
  2. Assign all your pins, so the Quartus II software fits your design correctly and gives correct timing analysis. To assign pin locations for the Stratix III development kit, run the top_custom_ddr2_controller_PinLocations.tcl file, which is provided with the design example or manually assign pin locations with the Pin Planner using the Stratix III FPGA Development Kit at the Altera website.

<note> If you are at the design exploration phase of your design cycle and do not have any PCB defined pin locations, you should still manually define an initial set of pin constraints, which can become more specific during your development process.

To manually assign pin locations, perform the following steps:

  1. Open Pin Planner. On the Assignments menu, click Pin Planner.
  2. Assign DQ and DQS pins.

a. To select the device DQS pin groups that the design uses, assign each DQS pin in your design to the required DQS pin in the Pin Planner. The Quartus II Fitter then automatically places the respective DQ signals onto suitable DQ pins within each group. To see the DQS groups in Pin Planner, right click, select Show DQ/DQS Pins, and click In ×8/×9 Mode. Pin Planner shows each DQS group in a different color and with a different legend: S = DQS pin, Sbar = DQSn pin, and Q = DQ pin.

<note> Most DDR2 SDRAM devices operate in ×8/×9 mode. However, some DDR2 SDRAM devices operate in ×4 mode. Refer to your specific memory device datasheet.

b. Select the DQ mode to match the DQ group width (number of DQ pins/number of DQS pins) of your memory device. DQ mode is not related to the memory interface width.

<note> The DQ group order and DQ pin order in each group is not important. However, you must place DQ pins in the same group as their respective strobe pin.

  1. Place DM pins in their respective DQ group.
  2. Place address and control command pins on any spare I/O pins ideally in the same bank or side of the device as the CK and CK_N pins.
  3. Ensure you place CK and CK_N pins on differential I/O pairs for the CK/CK# pin pair. To identify differential I/O pairs, right-click in Pin Planner and select Show Differential Pin Pair Connections. Pin pairs show a red line between each pin pair.

         <note> You must place CK and CK_N on a DIFFIO_RX pin pair, if your design uses differential DQS signaling.

  1. Place the clock_source pin on a dedicated PLL clock input pin with a direct connection to this design example's PLL and DLL pair—usually on the same side of the device as your memory interface. This recommendation reduces PLL jitter, saves a global clock resource, and eases timing and fitter effort.
  2. Place the global_reset pin (like any high fan-out signal) on a dedicated clock pin.

Board Trace Delay Models

For accurate I/O timing analysis, you must specify the board trace and loading information. This information should be derived and refined during your PCB development process of pre-layout (line) simulation and finally post-layout (board) simulation.

Compile Design and Verify Timing

Before compiling the design, set the top-level entity of the project. The design example top-level file is top_custom_ddr2_controller.v, which connects 13 other sub-modules or instances for a complete customized memory controller for DDR2.

To set the top-level file, perform the following steps:

  1. Open the top-level entity file, top_custom_ddr2_controller.v.
  2. On the Project menu, click Set as Top-Level Entity.

To compile the design, on the Processing menu, click Start Compilation. After successfully compiling the design, run the TimeQuest timing analyzer to verify the timing based on the SDC file. If the timing margin report shows negative hold time on the address and command datapath, adjusting the clock that is regulating the address and command output registers can improve the hold margin on the address and command datapath.

Perform Functional Simulation  

After you have compiled your design, set up and simulate the design in the ModelSim-Altera software by performing the following steps:

  1. Unzip the top_custom_ddr2_controller_msim.zip file to any directory on your PC. Obtain and copy the vendors memory Verilog HDL simulation model to the directory where the previous zip file was uncompressed. This can be retrieved from the Micron website. Get the ddr2.v, ddr2_mcp.v, and ddr2_parameters.vh memory model files from the Micron website and save them in the directory of this design example.
  2. Open the memory model file (ddr2.v) in a text editor and add the following define statements to the top of the file:

'define sg3
'define ×8
'define MAX_MEM

The three define statements prepare the DDR2 SDRAM interface model.

The first statement specifies the memory device speed grade as –3.

The second statement specifies the memory device width per DQS.

The third statement says to allocate memory for every address supported by the DDR2 model.

  1. Open the testbench (tb_top_custom_ddr2_controller.v) from the directory in a text editor, instantiate the downloaded memory model, and connect its signals to the rest of the design.
  2. Start the ModelSim® software.
  1. On the File menu, click Change Directory.
  2. Select the folder in which you unzipped the files.
  3. On the Tools menu, click Execute Macro.
  4. Select the top_custom_ddr2_controller_msim.do file and click Open. This is a script file for the ModelSim-Altera software to automate the necessary settings for the simulation.
  5. Verify the results shown in the Wave window.

Files

Original copy of EMI HB Volume 5 Chapter 1: Implementing Custom Memory Interface PHY

Design Example Files

Revision History

Initial Release: July 2011.

See Also

  1. List of designs using Altera External Memory IP

External Links

  1. Altera's External Memory Interface Solutions Center 
  2. Altera's External Memory Interface Handbook

Key Words

ALTDQ_DQS, DDR2, SDRAM, Design Example, External Memory, EMI, Stratix III, SIII

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